computer system and method for accessing a peripheral component interconnect express endpoint device

专利摘要:
"computer system, method for accessing an express peripheral component interconnect endpoint device and apparatus". The present invention relates to a computer system and a method for accessing a PCP-expressed peripheral component interconnect endpoint device. The computer system includes: a processor, a pcie bus, and an access server. the access server connects to the processor and the power endpoint device; The processor is configured to acquire an operation instruction, wherein the operation instruction instructs the processor to access the endpoint device by using the access server, and send an access request to the access server according to the operation instruction, wherein the access request instructs the access server to access the pcie endpoint device; and the access server is configured to send a processor access request response message after receiving the access request sent by the processor. Because the processor does not directly access the endpoint device to be accessed, but completes access by using the access server, the access server is able to return the processor access request response message. , thus preventing an mce reboot for the processor. 20131516v1 1/1 20131516v1
公开号:BR112013033792B1
申请号:R112013033792-3
申请日:2013-05-02
公开日:2018-12-04
发明作者:Ge Du
申请人:Huawei Technologies Co., Ltd.；
IPC主号:

专利说明:

(54) Title: COMPUTER SYSTEM AND METHOD FOR ACCESSING A DEPARTMENT DEPARTMENT DEPARTMENT FOR EXPRESS INTERCONNECTION OF PERIPHERAL COMPONENTS, COMPUTER, ACCESS SERVER AND PCIE EXCHANGER (73) Owner: HUAWEI TECHNOLOGIES CO., LTD .. Address: Huawei Administration Building, Bantian ,, Longgang District Shenzhen Gua, CHINA (CN) (72) Inventor: GE DU.
Validity Term: 20 (twenty) years from 5/2/2013, subject to legal conditions
Issued on: 12/04/2018
Digitally signed by:
Liane Elizabeth Caldeira Lage
Director of Patents, Computer Programs and Topographies of Integrated Circuits
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Invention Patent Descriptive Report for COMPUTER SYSTEM AND METHOD FOR ACCESSING AN EXPRESS END-DEVICE DEVICE FOR PERIPHERAL COMPONENTS, COMPUTER, ACCESS SERVER AND
PCIe EXCHANGER.
TECHNICAL FIELD
The modalities of the present invention relate to the field of computer technologies and, in particular, to a method for accessing an interconnecting endpoint device of peripheral components, a computer system and an apparatus.
BACKGROUND
An Express Peripheral Component Interconnect (Express Peripheral Component Interconnect, PCIe) is a high-performance system bus used in a computing and communication platform.
A PCIe bus is widely used in an interconnection system of a central processing unit (central processing unit, CPU) and a peripheral device and functions as a core service channel in a calculation and storage device. There can be multiple types of peripheral devices that interconnect with a CPU via a PCIe bus, such as a network interface card device or a solid state disk (Solid State Disk, SSD). Such devices are referred to as PCIe endpoint devices in this document.
A PCIe bus is widely used as a bus interface for a server or a storage system. During normal system operation, a PCIe endpoint device needs to be added or removed in a non-powered condition due to an expansion of connected capacity and a maintenance requirement, that is, an exchange requirement. The current PCIe exchange follows the following operating process: An operator initiates an exchange request at the press of a button; after understanding an exchange event, an exchange controller notifies all units that can access the endpoint device from
Petition 870180013615, of 02/20/2018, p. 4/65
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PCIe to interrupt access to the PCIe endpoint device and uninstall resources from the PCIe endpoint device where the exchange needs to be performed; and then the PCIe endpoint device is turned off and the operator removes the PCIe endpoint device.
Advance notification is required for the current exchange of a PCIe endpoint device to ensure normal system operation. However, recently, the PCIe bus has been gradually developed from inter-system interconnection to inter-system interconnection and applications, such as external cables, have increased. Cables are easily abnormally disconnected and therefore a condition in which a PCIe endpoint device is abnormally disconnected if advance notification occurs. Additionally, a scenario in which a user uses an SSD solid state drive to connect directly to a system occurs more and more broadly. The user can directly insert or remove the SSD disk without advance notification due to a user habit factor. For the mentioned condition where the PCIe endpoint device is suddenly and abnormally disconnected, if the CPU has initiated read and write instructions for the PCIe endpoint device, the relevant instructions will remain in a state of waits to be done; and when instructions to access the CPU's PCIe endpoint device accumulate continuously to a certain degree, the CPU considers the entire system to be abnormal and reports a machine check exception error (machine check exception, MCE). As a result, a system-wide restart is caused.
SUMMARY
The embodiments of the present invention propose a method for accessing an express peripheral component interconnection endpoint arrangement, a computer system and an apparatus to prevent a processor-generated restart after a PCIe endpoint device is disconnected from abnormal mode.
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In a first aspect, an embodiment of the present invention provides a computer system, which includes:
a processor; and a PCIe express peripheral component interconnect bus, configured to connect a PCIe endpoint device, where:
the computer system further includes an access server and the access server connects to the processor and the PCIe endpoint device;
the processor is configured to acquire an operating instruction, where the operating instruction instructs the processor to access the PCIe endpoint device using the access server; and sending an access request to the access server in accordance with the operating instruction, wherein the access request instructs the access server to access the PCIe endpoint device; and the access server is configured to send a response message from the processor access request after receiving the access request sent by the processor.
With reference to the first aspect, in a first possible deployment way, the computer system also includes: a drive module for the PCIe endpoint device, configured to generate the operation instruction according to a predefined interface to access the PCIe endpoint device, where the predefined interface for accessing the PCIe endpoint device points to the access server; and the processor is specifically configured to acquire the operating instruction generated by the drive module of the PCIe endpoint device.
With reference to the first aspect, in a second way of possible deployment, the computer system also includes: a drive module for a PCIe endpoint device and a host operating system, in which:
4/38 the PCIe endpoint device driver module is configured to invoke the host operating system in order to access the PCIe endpoint device;
the host operating system receives in response to the call by the driver module of the PCIe endpoint device and generates the operating instruction according to the predefined interface to access the PCIe endpoint device and the predefined interface to access the PCIe endpoint device points to the access server; and the processor is specifically configured to acquire the operating instruction generated by the host operating system.
With reference to the first aspect, the first possible deployment method of the first aspect or the second possible deployment method, in a third possible deployment method, the access server is further configured to perform access to the PCIe endpoint device from according to the access request.
In a second aspect, a method for accessing a PCIe expressed peripheral component interconnect endpoint device is provided, in which the PCIe endpoint device connects to a processor of a computer system via a bus PCIe, which includes:
acquire, by the processor, an operating instruction, in which the operating instruction instructs the processor to access the PCIe endpoint device using an access server;
send, by the processor, an access request to the access server according to the operating instruction, where the access request instructs the access server to access the PCIe endpoint device; and receive, by the processor, a response message for the access request sent by the access server.
With respect to the second aspect, in a first possible deployment, the processor acquires the operation instruction generated by a
5/38 PCIe endpoint device drive module according to a predefined interface for accessing the PCIe endpoint device, where the predefined interface for accessing the PCIe endpoint device points to the server access; alternatively, the processor acquires the operating instruction generated by a host operating system according to the predefined interface for accessing the PCIe endpoint device, where the predefined interface for accessing the PCIe endpoint device points to the access server. With reference to the second aspect or the first possible way of deploying the second aspect, in a second way of possible deployment, the operating instruction specifically instructs the processor to access the PCIe endpoint device using an access mechanism direct memory (Direct Memory Access, DMA); and the processor sends a data migration request to the DMA engine according to the operating instruction, where the data migration request instructs the DMA engine to migrate specific data in a PCIe engine memory to a PCIe engine memory. computer system or migrate specific data in the computer system memory to the PCIe endpoint device memory.
With reference to the second aspect, the first possible way of implanting the second aspect or the second possible method of implanting the second aspect, in a third possible way of implantation, the method further includes:
receiving, by the processor, a first notification message sent by the access server, where the first notification message indicates that the access server successfully accesses the PCIe endpoint device; and acquire, by the processor, an access result according to the first notification message.
With reference to the second aspect, the first way of planting the second aspect, or the second method of possible implantation of the second aspect, in a fourth way of possible implantation, the method further includes:
receiving, by the processor, a second notification message sent by the access server, where the second notification message indicates that the access server fails to access the PCIe endpoint device; and performing, by the processor, subsequent processing for an access failure according to the second notification message.
With reference to the fourth possible deployment method of the second aspect, in a fifth possible deployment method, the subsequent processing of the access failure includes:
determine, by the processor, a reason for the access server to fail to access the PCIe endpoint device and, if the reason for the access failure is that the PCIe endpoint device to be accessed is abnormally disconnected, stop , by the processor, access to the PCIe endpoint device.
In a third aspect, a computer is provided, which includes: a processor; and a memory configured to store a computer execution instruction, where:
when the computer is running, the processor executes the computer execution instruction stored in memory and communicates with an external computer device through a communications interface, so that the computer executes a method to access a point device peripheral component interconnect end expresses PCIe according to the second aspect.
In a fourth aspect, a computer-readable medium is provided, which includes: a computer execution instruction, in which a computer executes a method to access a PCIe express peripheral component interconnection endpoint device according to the second aspect when an e7 / 38 computer processor executes the computer execution instruction.
In a fifth aspect, a method for accessing a PCIe Express peripheral component interconnect endpoint device is provided, in which the PCIe endpoint device connects to a processor of a computer system via a bus PCIe, which includes:
receive a call instruction, where the innovation instruction indicates that the PCIe endpoint device needs to be accessed, and generate an operating instruction according to the predefined interface to access the PCIe endpoint device, at that the predefined interface for accessing the PCIe endpoint device points to an access server and the operating instruction is used to instruct the processor to access the PCIe endpoint device using the access server.
In a sixth aspect, an apparatus for accessing a PCIe express peripheral component interconnect endpoint device is provided, which includes:
a receiving module, configured to receive a call instruction, where the innovation instruction indicates that the PCIe endpoint device needs to be accessed; and a generation module, configured to generate, according to a predefined interface to access the PCIe endpoint device, an operating instruction to access the PCIe endpoint device, where the predefined interface to access the PCIe endpoint device points to the access server and the operating instruction is used to instruct the processor to access the PCIe endpoint device using the access server.
In a seventh aspect, a computer is provided, which includes: a processor; and a memory, configured to store an instruction of
8/38 computer execution, where:
when the computer is running, the processor executes the computer execution instruction stored in memory, so that the computer executes the following method:
receive a call instruction, where the innovation instruction indicates that the PCIe endpoint device needs to be accessed, and generate, according to a predefined interface to access the PCIe endpoint device, an operating instruction to access the PCIe endpoint device, where the predefined interface for accessing the PCIe endpoint device points to the access server and the operating instruction is used to instruct the processor to access the endpoint device end of PCIe using the access server.
In an eighth aspect, a computer-readable medium is provided, which includes: a computer execution instruction, in which the computer performs the following method when a computer processor executes the computer execution instruction:
receive a call instruction, where the innovation instruction indicates that the PCIe endpoint device needs to be accessed, and generate, according to a predefined interface to access the PCIe endpoint device, an operating instruction to access the PCIe endpoint device, where the predefined interface for accessing the PCIe endpoint device points to the access server and the operating instruction is used to instruct the processor to access the endpoint device end of PCIe using the access server.
In a ninth aspect, an access server is provided, where the access server applies to a computer system, the computer system includes a processor and a PCIe express peripheral component interconnect bus and the PCIe bus connects to
9/38 at least one PCIe endpoint device;
the access server connects to the processor and the PCIe endpoint device; and the access server is configured to isolate direct access between the processor and the PCIe endpoint device, receives a request to access the processor's PCIe endpoint device, and returns an access request response message to the processor.
In a tenth aspect, a PCIe exchanger is provided, in which the PCIe exchanger applies to a computer system, the computer system includes a processor and a PCIe express peripheral component interconnect bus and the PCIe bus is connected. if at least one PCIe endpoint device;
one port upstream from the PCIe exchanger connects to the processor via the PCIe bus and one port downstream from the PCIe exchanger connects to the PCIe endpoint device via the PCIe bus; and the access server according to the ninth aspect is incorporated into the PCIe exchanger.
In an eleventh aspect, a method for allocating resources on a PCIe express peripheral component interconnect endpoint device that accesses a computer system is provided, which includes:
reserve a specific portion of resources for each port to access the PCIe endpoint device, where the specific portion is greater than or equal to the amount of resource required from the PCIe endpoint device; and allocating, according to the specific reserved portion of resources, the specific reserved portion of resources on each port to access the PCIe endpoint device.
According to the eleventh aspect, in a first way of implantation, the specific portion is an amount of resource
10/38 required for a type of PCIe endpoint that has a maximum resource quantity requirement.
According to the eleventh aspect or the first possible deployment way of the eleventh aspect, in a second possible deployment way, the PCIe endpoint device that accesses the computer system and a processor constitute a PCIe field, where the PCIe field is configured with a corresponding PCIe tree; and the method also includes: writing to the PCIe tree the specific portion of resources allocated on each port to access the PCIe endpoint device.
According to the second possible way of implanting the eleventh aspect, in a third possible way of implantation, the method includes:
when each PCIe endpoint device is disconnected from the computer system, reserve the specific portion of resources that are allocated on each port to access the PCIe endpoint device and are written to the PCIe tree.
In a twelfth aspect, a computer system is provided, which includes:
a processor; and a PCIe express peripheral component interconnect bus, configured to connect to a PCIe endpoint device;
a basic BIOS input and output system, configured to reserve a specific portion of resources for each port to access the PCIe endpoint device, where the specific portion is greater than or equal to the amount of resources required from the point device PCIe endpoint; and a PCIe management module, configured to allocate, according to the specific portion of resources reserved by the BIOS, the specific reserved portion of resources for each port to access the PCIe endpoint device.
In the embodiments of the present invention, a processor no longer directly accesses a PCIe endpoint device to be accessed, but completes access with the use of an access server. The access server can isolate an impact brought about by abnormal disconnection of the PCIe endpoint device and return a response message from a processor access request, so that tasks in provisioning intermediate storage on the processor do not accumulate due to timeout, and therefore the processor prevents an MCE reset.
In the embodiments of the present invention, the system reserves and allocates a specific portion of resources on a port to access a PCIe endpoint device, so that the processor does not scan the PCIe endpoint device when the point device end point accesses the system. This prevents an entire system restart caused by an MCE error that can occur when the PCIe endpoint device accesses the computer system.
BRIEF DESCRIPTION OF THE DRAWINGS
To illustrate the technical solutions in the modalities of the present invention more clearly, the following briefly introduces the accompanying drawings required to describe the modalities or the prior art. Apparently, the accompanying drawings in the following description merely show some embodiments of the present invention and a person skilled in the art can still derive other designs from these attached drawings without creative effort.
FIG. 1 is a composition diagram of a computer system according to an embodiment of the present invention;
FIG. 2 is a diagram of the composition of program modules included in a memory according to an embodiment of the present invention;
FIG. 3 is a composition diagram of another system of
12/38 computer according to an embodiment of the present invention;
FIG. 4 is a composition diagram of another computer system according to an embodiment of the present invention;
FIG. 5 is a flow chart of a method according to an embodiment of the present invention;
FIG. 6 is a flow chart of another method according to an embodiment of the present invention;
FIG. 7 is a flow chart of another method according to an embodiment of the present invention;
FIG. 8 is a flow chart of another method according to an embodiment of the present invention;
FIG. 9 is a flow chart of another method according to an embodiment of the present invention;
FIG. 10 is a flow chart of another method according to an embodiment of the present invention;
FIG. 11 is a composition diagram of an apparatus for accessing a PCIe endpoint device according to an embodiment of the present invention; and FIG. 12 is a composition diagram of a computer according to an embodiment of the present invention.
DESCRIPTION OF MODALITIES
The embodiments of the present invention provide a method for accessing a peripheral component interconnection endpoint device, a computer system and an apparatus. When an interchange operation needs to be performed on a PCIe endpoint device, a system may not be notified in advance of preprocessing and a connection between the PCIe endpoint device and a processor is directly disconnected. At this time, an MCE restart risk does not occur on the processor. In the embodiments of the present invention, a condition in which the PCIe endpoint device is directly removed from the system and is disconnected due to a failure is collectively called
13/38 abnormal disconnection from the PCIe endpoint office. System architecture in one embodiment of the present invention
FIG. 1 is a composition diagram of a computer system according to an embodiment of the present invention. The computer system shown in FIG. 1 includes a CPU 110, memory 120 and a PCIe 130 endpoint device. The PCIe 130 endpoint device connects to CPU 110 via a PCIe 140 bus and can be inserted or removed from the system. computer. The PCIe endpoint device 130 includes multiple types, such as a graphics processing unit 131, a network interface card 132, a solid state disk 133, and a video acceleration component 134. Memory 120 is configured to store data, in which the stored data can be data acquired by the CPU of an external device or can also be program data that allows the CPU to work. Specifically, one or more program modules can be stored in memory and CPU 110 performs a related operation according to the computer execution instruction for a program module. The PCIe 130 endpoint device and CPU 110 on the computer system shown in FIG. 1 constitute a PCIe field and all devices in the PCIe field connect to CPU 110 via PCIe bus 140 and are controlled by CPU 110.
In the system architecture shown in FIG. 1, as shown in FIG. 2, the program modules in memory 120 can specifically include an application module 121, a drive module 122 and a host operating system Host Operation System (HOS) 123. Application module 121 generates a requirement to access a PCIe endpoint. Drive module 122 can call a corresponding HOS 123 interface (if an access interface is provided by HOS) according to the application module's requirement to access the PCIe endpoint device. HOS 123 generates an operating instruction according to in response to the call by the drive module, so that the CPU accesses or controls the corresponding PCIe endpoint positive dis14 / 38 according to the operating instruction. Generally speaking, a PCIe endpoint device corresponds to a trigger module (it is certainly possible that a drive module corresponds to multiple PCIe endpoint devices as long as each PCIe endpoint device is guaranteed to be equipped with a corresponding drive module). For example, according to the system architecture shown in FIG. 1, the drive modules of the PCIe endpoint devices in memory 120 may include a drive module 122-1 of the graphics processing unit, a drive module 122-2 of the NIC network interface card, a module drive 122-3 of the SSD solid state disk and a drive module 122-4 of the video acceleration component.
For example, if the application module generates a requirement to access an SSD solid state disk, according to a current method for accessing a PCIe endpoint device through the CPU, the SSD drive module 122-3 calls the HOS 123 after receipt in response to the call by application module 121; HOS 123 generates an operating instruction to CPU 110 according to a standard configured access interface, wherein the operating instruction includes an instruction from the device SSD 133 to be accessed and a related operating requirement; CPU 110 sends an access request to SSD 133 according to the SSD drive module 122-3 operating instruction, in order to require access to an SSD 133 register; if SSD 133 is disconnected abnormally, CPU 110 will not receive a response message from access request from CPU 110 of SSD 133 and at that time, the CPU considers the access task to be incomplete; and if such incomplete tasks accumulate to some degree on the CPU, the CPU considers the entire system to be abnormal and reports an MCE error for restart.
In this embodiment of the present invention, the method for accessing a PCIe endpoint device by the CPU is changed. The CPU no longer directly accesses the endpoint device from
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PCIe, but accesses the PCIe endpoint device using a third party. As shown in FIG. 1, an access server 160 is newly added to the system in this embodiment of the present invention, where access server 160 is used in place of CPU 110 to access the PCIe endpoint device and isolate an abnormal disconnect impact of the PCIe endpoint device on CPU 110. As shown in FIG. 1, CPU 110 no longer uses line 1 to access SSD 133, but uses line 2 and line 3 (line 1 is the Line shown in FIG., Line 2 is Line2 shown in FIG., The line 3 is Line3 shown in FIG. and the dashed lines of Line 3 to 3 shown in FIG are not actual connections, but are only used to visually illustrate the signal flow lines between each composition module). CPU 110 first acquires the operating instruction, where the operating instruction instructs the CPU to access SSD 133 using access server 160. Then, CPU 110 sends the access request to access server 160 via line 2. Access server 160 returns a response message from access request to CPU 110 via line 2. Subsequently, the access server performs access to the PCIe endpoint device according to the access request, or that is, it performs read and write operations in the SSD133 register via line 3. Thus, in one aspect, due to the fact that CPU 110 does not generate a direct signal relationship with the PCIe 130 endpoint device, it is invisible to CPU 110 if the PCIe 130 endpoint device is disconnected, that is, the PCIe endpoint device does not affect CPU 110 service processing; in another aspect, the access server 160 provided by this embodiment of the present invention can return a response message to CPU 110 after receiving the access instruction from CPU 110, so that the corresponding response message can always be received for the request. of access sent by CPU 110. Therefore, access tasks of CPU 110 do not accumulate due to non-completion of tasks, no MCE errors are generated and a system restart initiated by pe16 / 38
The CPU is avoided.
In this embodiment of the present invention, the method for accessing a PCIe endpoint device through the CPU can be changed by enhancing and improving a drive module corresponding to the PCIe endpoint device. When it is deployed by reconstructing the drive module corresponding to the PCIe endpoint device, an access interface is predefined in the drive module corresponding to the PCIe endpoint device, where the predefined access interface points to the access server; and when the driver module corresponding to the PCIe endpoint device determines that it needs to access the PCIe endpoint device, the driver module of the PCIe endpoint device generates a CPU operating instruction according to the default access interface, where the operating instruction instructs the CPU to access the PCIe endpoint device using the access server.
Additionally, changing the method for accessing a PCIe endpoint device through the CPU may have another deployment method. For example, the change is implemented by modifying the HOS. An access interface is predefined in HOS, where the predefined access interface points to the access server. When it determines that access to the PCIe endpoint device is required, the drive module of the PCIe endpoint device still calls HOS to access the PCIe endpoint device. After the HOS receives the call instruction sent by the activation of the PCIe endpoint device, due to the fact that the interface to access the PCIe endpoint device configured in the HOS has been predefined for the access server, the HOS generates the operating instruction, where the operating instruction instructs the CPU to access the PCIe endpoint device using the access server.
The following describes functions and forms of detailed deployment17 / 38 of the access server in accordance with this embodiment of the present invention. The access server according to this embodiment of the present invention includes an isolation function and an access server function. Acting as an isolation module, the access server needs to guarantee its independence from the PCIe endpoint device and also needs to guarantee its independence from the CPU. To maintain the independence of the PCIe endpoint device, it is necessary to ensure that the access server is not removed directly with the PCIe endpoint device and therefore the access server and the endpoint device PCIe endpoint needs to belong to different devices in physical configurations; to maintain CPU independence, it is primarily ensured that the access server has an independent processor. When the access server processor is independent of the system CPU, even if the PCIe endpoint device is removed directly, an impact on the access server module will not infect the CPU. Acting as a server module, the access server needs to deploy access to the PCIe endpoint device and return a response message from an access request received from the CPU, where the response message from the access request can be a confirmation response, a rejection response, or a failure response. However, regardless of any type of response message, the message indicates to the CPU that the access request sent by the CPU has been received. The CPU determines that a current task is complete after receiving the response message and can shut down a timer started for the task. In this way, a CPU task timeout shutdown mechanism remains normal and other messages in the intermediate provisioning storage on the CPU do not accumulate due to the timeout, thus preventing a MCE restart generated by the CPU.
Based on the consideration of the functions of the access server, the access server in the system can also be defined in multiple ways. In the system architecture shown in FIG. 1, the access server
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160 is defined in the computer system as a standalone and newly added device and the access server connects to the CPU and the PCIe endpoint device via the PCIe bus. In addition, the access server 160 can also be packaged with an existing device in the PCIe field for deployment. For example, access server 160 is packaged with the CPU as firmware.
The access server in this embodiment of the present invention can be deployed using existing hardware. For example, the access server is deployed using a direct memory access mechanism (Direct Memory Access, DMA). The access server can also be deployed using new hardware. For example, a software module that has an access server role is installed on a hardware device that has an independent processor.
Due to the fact that the access server in this modality of the present invention needs to return the response message of the CPU access request, during specific deployment, there are different ways to implement the access server function. One of the deployment ways is that a connection relationship between the access server and the CPU is guaranteed to be in a hold state, that is, the connection relationship between the two will not be disconnected or the access server is not interchangeable for the CPU. For example, a hardware device on which the access server is loaded or a hardware device that is used to deploy the access server is soldered to a PCB printed circuit board that connects to the CPU or an interface to connect the device of hardware on which the access server is loaded or the hardware device that is used to deploy the access server and the processor is secured using a connector.
FIG. 3 illustrates a computer system according to another embodiment of the present invention.
In the computer system shown in FIG. 3, except for a CPU, a PCIe bus and a PCIe endpoint device shown in FIG. 1, a PCIe 150 changer is also included. An
19/38 upstream port of the PCIe 150 changer connects to CPU 110 via a PCIe 140 bus and a downstream port provides a PCIe port for each PCIe endpoint device, where each PCIe port connects each PCIe endpoint device via the PCIe 140 bus. The PCIe 150 changer is configured to prorate data downstream to a PCIe port and corresponding and prorate data from each independent PCIe port to CPU 110 In the embodiment shown in FIG. 3, a newly added access server 160 is defined within the PCIe exchanger 150 and the access server 160 in this mode is deployed using a DMA mechanism. The PCIe 130 endpoint device connects to the PCIe 150 changer via the PCIe 140 bus. Due to the fact that the PCIe 150 changer and the PCIe 130 endpoint device belong to the different devices, removal directly from any PCIe endpoint device does not cause the removal of the PCIe 150 changer from the system, that is, it ensures that the access server 160 is not removed by removing the PCIe endpoint device as well deploying the independence of the access server 160 and that of the PCIe 130 endpoint device. Additionally, in this embodiment, due to the fact that the DMA engine has a processor independent, if any PCIe endpoint device is removed directly and even access to the DMA's PCIe endpoint device is affected, the DMA isolates the impact. Regardless of whether access to the PCIe endpoint device is successful, the DMA is guaranteed to return to CPU 110 a response message from an access request sent by CPU 110, thereby avoiding a problem with a CPU-initiated MCE reset.
It is also used as an example that an application module generates a requirement for access to an SSD 133 solid state disk. CPU 110 acquires an operating instruction generated by a drive module 122-3 of the SSD solid state disk, in that the operating instruction instructs CPU 110 to access the SSD 133 solid state disk
20/38 with the use of DMA. CPU 110 sends a data migration request to the DMA in accordance with the SSD solid state drive drive module 122-3 operating instruction, where the data migration request instructs the DMA engine to migrate specific data in a PCIe endpoint device memory to a computer system memory or migrate specific data in the computer system memory to the PCIe endpoint device memory. After receiving the data migration request from CPU 110, the DMA returns a response message from the data migration request to CPU 110, performs the data migration on the SSD 133 solid state disk, and after the data migration is complete , returns a notification message of completion of access to CPU 110, in order to instruct CPU 110 to acquire an access result.
Furthermore, due to the fact that the DMA in this modality of the present invention is incorporated into the PCIe 150 changer, the PCIe 150 changer can also be soldered on a PCB printed circuit board that connects to CPU 110 or an interface to connect the PCIe 150 changer and CPU 110 is fixed using a connector. This ensures that the DMA embedded in the PCIe 150 changer is not removed from the system and, therefore, ensures that the DMA can always return a response message from a CPU access request.
FIG. 4 illustrates a computer system according to another embodiment of the present invention;
In the embodiment shown in FIG. 4, is different from the embodiment shown in FIG. 3 due to the fact that an access server 160 is reconditioned to a CPU 110, where the access server 160 can be deployed using a DMA mechanism. Access server 160 is defined within CPU 110, that is, it ensures that access server 160 is not removed by removing a PCIe endpoint device, thus deploying independence for access server 160 and that of the PCIe 130 endpoint device. Additionally, in this mode, due to the fact that the
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DMA has a stand-alone processor, if any PCIe endpoint device is removed directly and even access to the PCIe endpoint device from the DMA is affected, the DMA isolates the impact so that CPU 110 is not infected. Regardless of whether access to the PCIe endpoint device is successful, the DMA is guaranteed to return to CPU 110 a response message from an access request sent by CPU 110, thereby avoiding a problem with a CPU-initiated MCE reset. A detailed access method in this embodiment is consistent with those described in the embodiments shown in FIG. 1 and FIG. 3 and therefore, no further details are provided in this document.
A method for accessing a PCIe endpoint device in the embodiments of the present invention can be implanted in a computer system shown in FIG. 1, in FIG. 3 or in FIG. 4. However, what is shown in FIG. 1, in FIG. 3 or in FIG. 4 is just an example that applies to the modalities of the present invention, but it is not a specific limitation in an application of the present invention. Other system modalities or application scenarios are not described in this order document. Additionally, the settings of an access server on a system shown in FIG. 1, in FIG. 3 or in FIG. 4 are just examples. Those skilled in the art can further define the newly added access server in the modalities of the present invention to another position in the system or use other technical means for deployment in accordance with a technical principle of the modalities of the present invention.
CPU 110 shown in FIG. 1, in FIG. 3 or in FIG. 4 is also just an example. For example, it can also be a specific integrated circuit. No matter what form, it implements a processor function in a computer system. The computer system in the embodiments of the present invention can still be a computational server or it can be a server that manages routes, such as a switch. A form of detailed implementation of the computer system is not limited in this embodiment of the present invention.
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Process for accessing a PCIe endpoint device
The following describes a process for accessing a PCIe endpoint device in accordance with an embodiment of the present invention, wherein the process is deployed by a newly added access server on a computer system. As shown in FIG. 5, a process for accessing a PCIe endpoint device in this embodiment of the present invention includes:
S501: A CPU acquires an operating instruction, where the operating instruction instructs the CPU to access the PCIe endpoint device using the access server on the computer system.
Specifically, the operating instruction can be generated by a PCIe endpoint device driver module. Due to the fact that the PCIe endpoint device driver module has predefined an interface to access the PCIe endpoint device as the access server, when an upper layer application module generates a requirement for access to a PCIe endpoint device, the drive module of the PCIe endpoint device generates an operating instruction to access the PCIe endpoint device, where the operating instruction instructs the CPU to access the device of the PCIe endpoint to be accessed using the access server on the computer system. Alternatively, the operating instruction can also be generated by an HOS in the computer system. HOS has predefined the interface to access the PCIe endpoint device as the access server. When the upper layer application module generates a requirement to access a PCIe endpoint device, the PCIe endpoint device trigger module calls HOS and HOS generates the operating instruction according to the interface predefined access, where the operating instruction instructs the CPU to access the PCIe endpoint device to be accessed using the access server on the computer system.
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S502: The CPU sends an access request to the access server according to the operating instruction, where the access request instructs the access server to access the PCIe endpoint device.
S503: The access server returns a response message from the CPU access request after receiving the access request sent by the CPU.
The access request response message can be a confirmation response, a rejection response, or a failure response. However, regardless of any type of response message, the message indicates to the CPU that the access request sent by the CPU has been received. The CPU determines that a current task is complete after receiving the response message and can shut down a timer started for the task. This way, a CPU task timeout shutdown mechanism keeps normal.
In the process, a CPU does not directly access a PCIe endpoint device to be accessed, but it does complete access using an access server. The access server can isolate an impact brought about by abnormal disconnection of the PCIe endpoint device and the access server returns a response message from a CPU access request, so that the tasks in provisioning intermediate storage on the CPU do not accumulate until the timeout, thus avoiding an MCE reset for the CPU.
Furthermore, as shown in FIG. 6, in another process of the present invention, a process for an access server to access a PCIe endpoint device includes:
S601 to S603: These steps are the same as steps S501 to S503 and therefore, no further details are provided in this document.
S604: The access server initiates an operation to access the PCIe endpoint device according to the CPU access request.
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S605: The access server determines whether the access operation initiated for the PCIe endpoint device is successful; if the access operation is successful, perform step 606; and if the access operation fails, perform step 608.
S606: The access server sends a first CPU access completion notification message.
S607: The CPU acquires an access result after receiving the first notification message.
The CPU can also notify an upper layer module of the completion of access according to the access result.
S608: The access server sends a second CPU failure access notification message.
S609: The CPU performs subsequent processing for the access failure after receiving the second notification message.
Specifically, subsequent processing for an access failure includes: determining a reason for the access server to fail to access the PCIe endpoint device; if the reason for the access failure is that the PCIe endpoint device to be accessed has been abnormally disconnected, interrupt, by the CPU, access to the PCIe endpoint device; and if the reason for the access failure is that the access server has failed, reset the access server by the CPU or send a notification indicating that the access server is failing in order to rectify the failure of the access server .
After interrupting access to the PCIe endpoint device, the CPU can still notify the top layer module to interrupt access to the PCIe endpoint device.
The process describes a method for accessing a PCIe endpoint device in this embodiment of the present invention. In the method, an access server, in place of the CPU, accesses the PCIe endpoint device and returns a response message from a CPU access request, thereby preventing a system-wide restart caused by an MCE error that is generated by the CPU. Ade25 / 38 more, when the access server fails to access the PCIe endpoint device, the access server notifies the CPU of a message of an access failure. The CPU performs a fault diagnosis and when it determines that the access failure is caused by abnormal disconnection of the PCIe endpoint device to be accessed, it interrupts access to the PCIe endpoint device to be accessed, thereby preventing a waste of resources that is caused when the system continues to perform repeated access that cannot be successful.
In combination with the mode of a computer system shown in FIG. 3 or in FIG. 4, when an access server is deployed using a DMA mechanism, an upper layer application module generates a read operation required for an SSD, a specific access process is shown in FIG. 7, including:
S701: A CPU in a computer system obtains an operating instruction, where the operating instruction carries an access interface and access content, the access interface points to the DMA mechanism, the access content indicates that an object access is the SSD and access is a read operation and indicates a source address for the read operation; and the access content may also indicate an extension of the read operation, but in general the extension of the read operation may be subject to a standard extension in the system.
When an upstream endpoint generates a read operation requirement for the SSD device, an SSD drive module receives in response to the call by the upstream end point and generates an operating instruction to access a PCIe endpoint according to a predefined access interface.
A detailed method of deploying the operating instruction sent by the drive module to the CPU can be in yet another way. For example, the operation instruction carries indications that indicate that the object of access is the SSD and the access is a read operation and that indicates a start address of the read operation; additionally, an in26 / 38 statement is newly added in the operating instruction to instruct access to the SSD to be deployed by operating the DMA mechanism.
S702: The CPU sends a data migration request to the DMA engine according to the operating instruction, where the data migration request is used to instruct the DMA engine to migrate specific data in a point device memory end point to a computer system memory.
Specifically, after acquiring the operating instruction from the SSD drive module, the CPU applies the computer system's memory to a destination address for the read operation and sends the data migration request to the DMA engine after acquiring the destination address of the read operation, where the data migration request indicates the source address, destination address, and extent of the read operation, in order to instruct the DMA mechanism to migrate data from the read operation extension reading from the source address of the read operation to the destination address of the read operation.
S703: The DMA engine returns a data migration request response message to the CPU after receiving the data migration request from the CPU and the CPU does not time out the data migration request after receiving the response message of the data migration request, in order to ensure that other messages in the provisioning intermediate storage on the CPU will not cause the CPU to generate an MCE reset due to accumulation.
S704: The DMA engine initiates a read request to the SSD device, where the read request carries the source address of the read operation and the read operation is used to request a record value corresponding to the source address of the read operation to be read in a DMA mechanism provision buffer.
S705: The DMA mechanism determines whether the read request is executed successfully; if the read request is executed successfully, perform step 706; and if the read request fails to be cut, execute step 709.
S706: The DMA engine writes data to its own provisioning intermediate storage at the destination address of the read operation according to a write request.
S707: The DMA engine sends a first notification message to the CPU, where the first notification message can be specifically the first MSI interrupt (Message Signaled Interrupts, MSI) to notify the CPU that access is complete.
S708: The CPU reads the data from the destination address of the read operation after receiving the first MSI interrupt message and can notify the drive module of the SSD device that access is complete.
S709: The DMA engine sends a second notification message to the CPU, where the second notification message can be specifically the second MSI interrupt to notify the CPU that access has failed.
S710: The CPU performs subsequent processing for the access failure after receiving the second MSI interrupt message.
Specifically, the subsequent processing of an access failure includes: initiating a diagnosis on the DMA engine to determine whether the DMA engine is at fault;
if the DMA engine fails, reset the DMA engine by the CPU or send a notification indicating that the DMA engine has failed in order to recover from the DMA engine failure; and if the DMA mechanism has not failed, determine that a cause of the access failure is that the SSD device is normally disconnected and interrupt access by the CPU to the SSD device.
In addition, the CPU can also instruct the drive module of the SSD device to interrupt access to the SSD device.
In another aspect, with reference to the embodiment of a computer system shown in FIG. 3 or in FIG. 4, when an access server is deployed using a DMA mechanism, an access module
28/38 upper layer application generates a write operation requirement for the SSD, a specific access process is shown in FIG. 8, including:
S801: A CPU acquires an operating instruction generated by an SSD drive module, where the operating instruction carries an access interface and access content, the access interface points to the DMA mechanism and the access content indicates that the access object is the SSD device and the access is a write operation and indicates a source address and a destination address of the write operation.
A detailed method of deploying the operating instruction sent by the drive module to the CPU can be in yet another way. For example, the operation instruction carries indications that indicate that the access object is the SSD and the access is a write operation and which indicates a source address and the destination address of the write operation; in addition, an indication is newly added in the operating instruction to instruct access to the SSD to be deployed by operating the DMA mechanism.
S802: ACPU sends a request for access to the DMA engine according to the SSD drive module operating instruction, where the data migration request is used to instruct the DMA engine to migrate specific data into a computer system to a PCIe endpoint device memory.
Specifically, the CPU sends a data migration request to the DMA engine after acquiring the SSD drive module operating instruction, where the data migration request indicates the source address, the destination address and an extension of the write operation, in order to instruct the DMA mechanism to migrate data from the write operation extension from the source address of the writing operation to the destination address of the writing operation.
S803: The DMA engine returns a response message from the data migration request to the CPU after receiving the data migration request from the CPU.
S804: The DMA engine initiates a read request to the source address of the write operation in order to read data from the source address into a DMA engine provision buffer.
S805: The DMA mechanism initiates a write request to the SSD device after the source address data has been read in its own provision intermediate storage, where the write request carries the destination address of the writing operation and the the write request is used to write data to the DMA engine's provisioning buffer in a record corresponding to the destination address.
S806: The DMA mechanism determines whether the deed request is successfully executed; if the deed request is successfully executed, perform step 807; and if the deed request fails to be executed, perform step 809.
S807: The DMA engine initiates the first interrupt from MSI (Message Signaled Interruptions, MSI) to the CPU to notify the CPU that access is complete.
S808: The CPU understands that the write operation is complete after receiving the first MSI interrupt message and can also notify the drive module of the SSD device that access is complete.
S809: The DMA engine initiates the second MSI interrupt to the CPU to notify the CPU that access has failed.
S810: The CPU performs subsequent processing for the access failure after receiving the second MSI interrupt message.
Specifically, the subsequent processing of an access failure may include: starting a diagnosis on the DMA engine to determine whether the DMA engine is defective;
If the DMA engine is defective, restart the
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DMA or send a notification that indicates that the DMA engine is defective in order to recover from the DMA engine failure; and
If the DMA engine is not defective, determine that a cause of the access failure is that the SSD device is abnormally disconnected, and interrupt access by the CPU to the SSD device.
In addition, the CPU can further instruct the drive module of the SSD device to interrupt access to the SSD device.
The processes shown in FIG. 7 and in FIG. 8 describe the method processes for a DMA engine to complete reading or writing to an SSD device in the embodiments of the present invention. In the read or write method, the DMA engine, instead of the CPU, accesses the PCIe endpoint device and returns a response message from the CPU access request, so that the CPU does not generate an MCE error and a system-wide restart is avoided. Additionally, when the DMA engine fails to mitigate data from the SSD device, the DMA engine notifies the CPU of an access failure message, the CPU performs a failure diagnosis and when it determines that the access failure is due to when the SSD device is directly removed from the system or is defective, interrupting access to the SSD device, the self thus avoids a waste of resources that is caused when the system continues to perform repeated access that cannot be successful.
In addition, in this embodiment of the present invention, a method for a CPU to access a PCIe endpoint device can be changed by updating or enhancing a drive module that corresponds to the PCIe endpoint device or a system host operating. If the drive module that corresponds to the PCIe endpoint device is used to change the method for a CPU to access a PCIe endpoint device, the following process can be included:
S901: The exe / 38 PCIe shaking device driver module receives a call instruction from an upper layer application module, where the calling instruction indicates that the PCIe endpoint device needs to be accessed .
S902: The drive module corresponding to the PCIe endpoint device generates an operating instruction according to a predefined interface to access the PCIe endpoint device, where the predefined interface to access the PCIe endpoint device PCIe endpoint points to an access server, and the operation instruction is used to instruct the CPU to access the PCIe endpoint device by using the access server.
If a host operating system is configured to change the method for a CPU to access a PCIe endpoint device, the following process can be included:
S1001: The drive module that corresponds to the PCIe endpoint device receives a call instruction from an upper layer application module, where the call instruction indicates that the PCIe endpoint device needs to be accessed.
S1002: The drive module that corresponds to the PCIe endpoint device calls the host operating system, where the calling instruction indicates that the PCIe endpoint device needs to be accessed.
S1003: The host operating system generates an operating instruction according to a predefined interface for accessing the PCIe endpoint device, where the predefined interface for accessing the PCIe endpoint device points to an access server, and the operating instruction is used to instruct the CPU to access the PCIe endpoint device by using the access server.
APPLIANCE IN A MODE OF THE PRESENT INVENTION
As shown in FIG. 11, an apparatus for accessing a Component32 / 38 interconnect PCIe endpoint device expressly provided in an embodiment of the present invention includes:
a receiving module 1101, configured to receive a call instruction, where the call instruction indicates that the PCIe endpoint device needs to be accessed; and a generation module 1102, configured to generate, according to a predefined interface for accessing the PCIe endpoint device, an operating instruction for accessing the PCIe endpoint device, where the predefined interface for accessing the PCIe endpoint device points to an access server, and the operating instruction is used to instruct the CPU to access the PCIe endpoint device by using the access server.
Specifically, the access device can be a driver module for the PCIe endpoint device or a host operating system of the computer system.
FIG. 12 is a structural composition diagram of a computer according to an embodiment of the present invention. The computer in this embodiment of the present invention can include:
a processor 1201, a memory 1202, a system bus 1204, and an interface for communications 1205. CPU 1201, memory 1202, and the interface for communications 1205 connect and complete communications with each other using the system bus 1204.
Processor 1201 can be a single-core or multiple-core central processing unit or a specific integrated circuit, or is configured as one or more integrated circuits in that embodiment of the present invention.
Memory 1202 can be a high speed RAM memory or it can be a non-volatile memory (non-volatile memory), such as at least one magnetic disk memory.
Memory 1202 is configured to store a computer's execution instruction 1203. Specifically, the execution instruction
33/38 of computer 1203 may include a program code.
When the computer is in effect, processor 1201 performs instruction to execute computer 1203 and a method process shown in any one of FIG. 5 to FIG. 10 can be performed. COMPUTER SYSTEM TO ACCESS A DEVICE FROM
PCIe END POINT
When a PCIe endpoint device is removed from a computer system, it is possible that it will be inserted into the computer system again subsequently. Additionally, a condition that a new PCIe endpoint device needs to connect to a computer system in a state of health also exists. For example, like the popularity of an SSD device, a phenomenon that a user directly inserts or removes an SSD device occurs more and more often. In the prior art, when any PCIe endpoint device is powered on and connected to the system, a CPU initiates a resource allocation and scanning process for the PCIe endpoint device; in a process where the CPU scans the newly powered PCIe endpoint device, if the PCIe endpoint device is directly removed from the system, it is possible for the CPU to report an MCE error, which causes a system restart. To avoid the problem, this embodiment of the present invention presents a new solution for allocating resources to a PCIe endpoint device, so that the CPU does not need to scan or allocate resources to the newly powered PCIe endpoint device when the PCIe endpoint device has recently been powered on and connected to the system.
During computer system startup, a basic input-output system (Basic Input-Output System, BIOS) needs to reserve resources for each device in the system. For the PCIe endpoint device, the BIOS scans each port to access a PCIe endpoint device. When it finds a PCIe endpoint device through the scan, the BIOS reads a record
34/38 corresponding to the PCIe endpoint device and reserves resources correspondingly according to a request from the PCIe endpoint device, for example, reserves bus resources and memory address resources. Specifically speaking, the port for accessing a PCIe endpoint device described in this embodiment of the present invention can be a downlink port of a PCIe exchanger or a downlink port of a north bridge in the system.
In the solution for allocating resources to a PCIe endpoint device provided in this embodiment of the present invention, a resource reservation method for the computer system BIOS is different from that in the prior art. During computer system startup, the BIOS does not reserve resources according to an actual demand for a PCIe endpoint device found through the scan, but reserves a specific portion of resources for each port to access a point device. end of PCIe, where the specific portion is greater than or equal to a requested amount of resource from the PCIe endpoint device, and preferably the specific portion may be a resource quantity demand for a type of point device endpoint that has a maximum resource quantity demand. For example, the BIOS scans each port to access a PCIe endpoint device on the computer system, and regardless of whether a PCIe endpoint device is found by scanning and no matter what type of endpoint device PCIe endpoint is found through scanning, specifies that each port to access a PCIe endpoint device can be subsequently accessed by the type of PCIe endpoint device that has a maximum resource quantity demand. If 10 types of PCIe endpoint devices can be used in the current system and the one that has a maximum resource quantity demand is an SSD device that requires 10M memory resources that cannot be pre-obtained and 3 buses35 / 38 PCIe ports, the BIOS reserves, for each port to access a PCIe endpoint device, 10M resources that cannot be obtained and 3 PCIe bus resources.
Second, after the BIOS reserves resources, a computer system's PCIe management module allows all PCIe endpoint devices managed by a CPU in the computer system and the PCIe exchanger to constitute a PCIe field and configure a corresponding PCIe tree from the PCIe field, where the PCIe tree is used to describe each layer of the connection relationships of each PCIe endpoint device in the PCIe field to the CPU and a resource configuration condition for each PCIe endpoint device. Because the BIOS has reserved a specific portion of resources for each port to access a PCIe endpoint device, when loading each port to access a PCIe endpoint device, the PCIe management module does not scan a demand for actual resource quantity from the port's PCIe endpoint device, but allocates resources according to a BIOS resource reservation condition, that is, allocates a specific portion of resources reserved by the BIOS for each port to access a PCIe endpoint device, and writes a condition to allocate the specific portion of resources in the PCIe tree.
Additionally, when a PCIe endpoint device is defective or disconnected from the computer system, the PCIe management module does not release the specific portion of resources allocated to the de-energized PCIe endpoint device when it determines that the PCIe endpoint is disconnected. In addition, the architecture of the PCIe tree remains unchanged, that is, the connection relationship and resource configuration condition of the disconnected PCIe endpoint device are retained in the PCIe tree. Thus, because the features and connection relationship of the PCIe endpoint device have been configured in the PCIe field, when the
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PCIe is powered up and accesses the PCIe field, the PCIe management module notifies a corresponding drive module that the PCIe endpoint device is powered up and the PCIe endpoint device completes access to the PCIe field from the computer system. In this solution, when the PCIe endpoint device is powered up, the CPU does not need to scan the PCIe endpoint device, thereby preventing a system-wide reboot caused by an MCE error that can occur when the PCIe endpoint device accesses the computer system.
Persons skilled in the art can understand that each aspect of the present invention or a possible way of implementing each aspect can be specifically implanted as a system, a method, or a computer program product. Therefore, each aspect of the present invention or possible ways of implementing each aspect may use forms of a complete hardware modality, a complete software modality (which includes firmware, resident software, and the like), or a modality that combines software and hardware. , which is collectively called a circuit, module, or system in this document. In addition, each aspect of the present invention or possible ways of implementing each aspect may use a form of a computer program product, wherein the computer program product refers to a computer-readable program code in a readable medium. per computer.
The computer-readable medium can be a computer-readable signal medium or a computer-readable memory medium. The computer-readable memory medium includes, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or any appropriate combination thereof, such as random access memory (RAM), a read-only memory, an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, and a portable read-only memory (CD-ROM).
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A computer's processor reads the computer-readable program code stored in the computer-readable medium, so that the processor is able to perform the function actions stipulated in each step or combinations of each step in a flowchart and a device that deploys function actions stipulated in each block or a combination of blocks in the block diagram is generated.
Computer-readable program code can be completely executed on a user's computer, partially executed on the user's computer, partially executed on the user's computer and partially executed on a remote computer when functioning as a standalone software package, or completely executed on the remote computer or a server. It should also be noted that, in some alternative deployment solutions, functions indicated at each step in the flowchart or in each block of a block diagram may not occur in a sequence indicated in the flowchart or diagram. For example, depending on the functions involved, two steps or two blocks shown one after the other can be performed at the same time in practice, or sometimes the blocks are executed in an inverse sequence.
People of ordinary skill in the art may be aware that, in combination with the examples described in the modalities that are revealed in this specification, algorithm units and steps can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether the functions are performed by hardware or software depends on particular applications and conditions of design restriction of technical solutions. People skilled in the art can use different methods to implement the functions described for each particular application, but it should not be considered that the deployment goes beyond the scope of the present invention.
The aforementioned descriptions are merely specific embodiments of the present invention, but are not intended to limit the scope of protection of the present invention. Any ready-made variation or replacement38 / 38 understood by a person skilled in the art within the technical scope disclosed in the present invention should be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be subject to the scope of protection of the claims.
1/11

权利要求:
Claims (11)
[1]
1. Computer system characterized by the fact that it comprises:
a processor (110); and
5 a PCIe peripheral component interconnect express bus (140), configured to connect a PCIe endpoint device (130), where:
the computer system further includes an access server (160), and the access server (160) connects the processor (110) and the PCIe endpoint device (130);
the processor (110) is configured to acquire an operating instruction, wherein the operating instruction instructs the processor to access the PCIe endpoint device (130) through the access server (160); and send an access request to the access server
15 (160) according to the operating instruction, wherein the access request instructs the access server (160) to access the PCIe endpoint device (130); and the access server (160) is configured to send an access request response message to the processor (110) regardless of whether access to the PCIe endpoint device (130) is successful and after receiving the request access message sent by the processor (110), wherein the response message for the access request is to indicate to the processor (110) that the access server (160) has received the access request;
The processor 110 is further configured to turn off a timer initiated for the access request after receiving the response message from the access request.
[2]
2. Computer system, according to claim 1, characterized by the fact that the computer system still comprises:
30 a drive module (122) of the PCIe endpoint device (130), configured to receive a call instruction to access the PCIe endpoint device (130), and
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2/11 generate the operating instruction according to a predefined interface for accessing the PCIe endpoint device (130), where the predefined interface for accessing the PCIe endpoint device (130) points to the access (160); and
5 the processor (110) is specifically configured to acquire the operating instruction generated by the drive module (122) of the PCIe endpoint device (130).
[3]
3. Computer system, according to claim 1, characterized by the fact that it still comprises: a drive module (122) of the PCIe endpoint device (130) and a host operating system (123), in what:
the drive module (122) of the PCIe endpoint device (130) is configured to receive a call instruction to access the PCIe endpoint device (130) and
15 calling the host operating system (123) to perform access to the PCIe endpoint device (130);
the host operating system (123) is configured to answer the call made by the drive module (122) of the PCIe endpoint device (130) and generate the operating instruction
20 according to a predefined interface for accessing the PCIe endpoint device (130), wherein the predefined interface for accessing the PCIe endpoint device (130) points to the access server (160); and the processor (110) is specifically configured to acquire
25 the operating instruction generated by the host operating system (123).
[4]
4. Computer system according to any one of claims 1 to 3, characterized in that the access server (160) is further configured to access the PCIe endpoint device (130) according to the request access.
30 5. Computer system, according to claim 4, characterized by the fact that:
the access server (160) is implemented by a search engine
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Direct memory access DMA;
the processor (110) is configured to send an access request to the access server (160) according to the operating instruction which is as follows:
[5]
5 the processor (110) is specifically configured to send a data migration request to the DMA engine according to the operating instruction; and the access server (160) is configured to access the PCIe endpoint device (130) according to the
10 access which is as follows:
the DMA engine is specifically configured to, according to the data migration request, perform one of: migrate specific data in a memory of the PCIe endpoint device (130) to a memory (120) of the computer system , and migrate
15 specific data in memory (120) of the computer system to the memory of the PCIe endpoint device (130).
[6]
6. Computer system according to claim 4 or 5, characterized by the fact that:
the access server (160) is further configured to send an
20 first notification message to the processor (110), wherein the first notification message indicates that access to the PCIe endpoint device (130) is successful; and the processor 110 is further configured to acquire an access result after receiving the first notification message.
7. Computer system according to claim 4 or
5, characterized by the fact that:
the access server (160) is further configured to send a second notification message to the processor (110), wherein the second notification message indicates that access to the access point device
30 PCIe end (130) fails; and the processor (110) is further configured to perform subsequent processing for an access failure after receiving the second
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4ir notification message.
8. Computer system according to claim 7, characterized by the fact that the processor (110) is further configured to perform subsequent processing for an access failure after receiving the second notification message, which is as follows:
the processor (110) is configured to determine, after receiving the second notification message, a reason for the access server (160) to fail to access the PCIe endpoint device (130); and
10 if the reason for the access failure is that the PCIe endpoint device (130) is abnormally disconnected, the processor (110) is configured to interrupt access to the PCIe endpoint device (130).
9. Computer system, according to claim 8, characterized by the fact that it still comprises: a PCIe management module, in which:
the PCIe management module is configured to acquire a notification indicating that the PCIe endpoint device (130) is abnormally disconnected and reserve allocated resources
20 to the PCIe endpoint device (130).
Computer system according to any one of claims 1 to 9, characterized by the fact that the access server (160) is packaged with the processor (110).
11. Computer system according to any one of the claims 1 to 9, characterized by the fact that the access server (160) is fixedly connected to the processor (110); and the access server (160) is configured to send a response message from the access request to the processor (110) by using the fixed connection to the processor (110).
12. Computer system according to claim 11, characterized by the fact that the access server (160) connects fixedly to the processor (110) comprises:
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5/11 the access server (160) is soldered on a printed circuit board that connects to the processor (110), and the access server (160) is fixedly connected to the processor (110) by using firmware connection.
13. Computer system according to claims 1 to 9, characterized by the fact that the computer system still comprises: a PCIe changer (150), in which a port upstream of the PCIe changer (150) is connects to the processor (110) via the PCIe bus (140) and a port downstream from the PCIe changer (150) connects
10 to the PCIe endpoint device (130) via the PCIe bus (140).
14. Computer system according to claim 13, characterized by the fact that the access server (160) is packaged inside the PCIe exchanger (150).
15. Computer system according to claim 14, characterized by the fact that the PCIe exchanger (150) satisfies one of the following: the PCIe exchanger (150) is soldered on a printed circuit board that connects to the processor (110), and the PCIe exchanger (150) connects fixedly to the processor (110) using connection firmware.
16. Method for accessing an express PCIe peripheral component interconnect endpoint device, in which a processor (110) from a computer system connects to the PCIe endpoint device (130) via a bus. PCIe (140), characterized by the fact that it comprises the steps of:
25 acquire (501, 601), from the processor (110), an operating instruction, in which the operating instruction instructs the processor (110) to access the PCIe endpoint device (130) by using a server. access (160);
send (502, 602), through the processor (110), a request for
30 accessing the access server (160) according to the operating instruction, wherein the access request instructs the access server (160) to access the PCIe endpoint device (130); and
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6/11 receive (503, 603), by the processor (110), a response message from the access request sent by the access server (160), in which the response message is sent regardless of whether access to the point device PCIe endpoint (130) is successful and is
5 to indicate to the processor (110) that the access server (160) has received the access request;
disconnecting, by the processor (110), a timer initiated for the access request after receiving the response message from the access request.
17. Method for accessing an express PCIe peripheral component interconnect endpoint device according to claim 16, characterized by the fact that acquiring (501, 601) by the processor (110), an operating instruction comprises one of:
acquire, by the processor (110), the operation instruction generated
15 via a drive module (122) of the PCIe endpoint device (130) according to a predefined interface for accessing the PCIe endpoint device (130), wherein the predefined interface for accessing the PCIe endpoint device (130) PCIe endpoint (130) points to the access server (160); and
20 acquire, by the processor (110), the operation instruction generated by a host operating system (123) according to a predefined interface to access the PCIe endpoint device (130), where the predefined interface to access the PCIe endpoint device (130) points to the access server (160).
18. Method for accessing an express endpoint device for interconnecting PCIe peripheral components according to claim 16 or 17, characterized in that the access server (160) is implemented by an access DMA engine straight from memory, and the operation instruction specifically instructs the processor
30 (110) accessing the PCIe endpoint device (130) by using the DMA engine; and sending (502, 602), by the processor (110), a request
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[7]
7/11 access to the access server (160) according to the operating instructions comprises:
send, through the processor, a data migration request to the DMA engine according to the operating instruction, where the data migration request instructs the DMA engine to migrate specific data in a PCIe engine memory to a computer system memory or migrate specific data in the computer system memory to the PCIe endpoint device memory (130).
19. Method for accessing an endpoint device10 of PCIe peripheral component interconnect express according to claim 18, characterized in that the operating instruction still indicates that a type of access is a read operation and indicates a source address of the read operation and a length of the read operation; and
15 the sending (502, 602), by the processor (110), of a data migration request to the DMA engine according to the operating instruction comprises:
acquire, by the processor (110), a destination address of the read operation allocated by the computer system memory; and
20 send, through the processor (110), the data migration request to the DMA engine, in which the data migration request loads the source address of the read operation, the destination address of the read operation, and the length of the read operation, in order to instruct the DMA engine to migrate data of the length of the read operation
25 from the source address of the read operation to the destination address of the read operation.
20. Method for accessing an express PCIe peripheral component interconnection endpoint device according to claim 18, characterized in that the operating instruction still indicates that a type of access is a write operation and indicates a source address of the write operation, a destination address of the write operation, and a length of the write operation; and
Petition 870180144672, of 10/25/2018, p. 10/18
[8]
8/11 the sending (502, 602), by the processor (110), of a data migration request for the DMA engine according to the operating instruction comprises:
send, through the processor (110), the data migration request to the DMA engine, where the data migration request loads the source address of the write operation, the destination address of the write operation, and the length of the write operation, in order to instruct the DMA engine to migrate data of the length of the write operation from the source address of the write operation to the address
10 destination of the write operation.
21. Method for accessing an express PCIe peripheral component interconnect endpoint device according to claim 16 or 17, characterized by the fact that it further comprises:
15 receives, by the processor (110), a first notification message sent by the access server (160), wherein the first notification message indicates that the access server (160) accesses the PCIe endpoint device (130 ) successfully; and acquire, by the processor (110), an access result of
20 according to the first notification message.
22. Method for accessing an express PCIe peripheral component interconnection endpoint device according to any one of claims 16 to 20, characterized by the fact that it further comprises:
25 receiving, by the processor (110), a second notification message sent by the access server (160), wherein the second notification message indicates that the access server (160) fails to access the PCIe endpoint device (130); and perform, by the processor (130), subsequent processing
30 for an access failure according to the second notification message.
23. Method for accessing an endpoint devicePetition 870180144672, 10/25/2018, pg. 11/18
[9]
9/11 of PCIe peripheral component interconnection express, according to claim 22, characterized by the fact that the execution of the subsequent processing for an access failure comprises:
determine, by the processor (110), a reason for the access server 5 (160) to fail to access the PCIe endpoint device (130), and whether the reason for the access failure is that the endpoint device PCIe (130) is abnormally disconnected, interrupt, by the processor (110), access to the endpoint device from
PCIe (130).
[10]
10 24. Method for accessing an express PCIe peripheral component interconnect endpoint device according to claim 23, characterized by the fact that it further comprises:
acquire a notification indicating that the PCIe endpoint device (130) is abnormally disconnected and reserve resources allocated to the PCIe endpoint device (130).
25. Computer (1200) comprising:
a processor (1201), a memory (1202), a bus (1204), and an interface for communications (1205), in which:
memory (1202) is configured to store an instruction
20 computer execution (1203), the processor (1201) connects to memory (1202) via the bus (1204), and when the computer (1200) is running, the processor (1201) executes the execution instruction computer stored in memory (1202), characterized by the fact that the computer (1200) executes the method for accessing as defined in any one of claims 16 to 24.
26. Access server, where the access server applies to a computer system, characterized by the fact that the computer system comprises a processor and a PCIe peripheral component interconnect express bus, and the PCIe bus is
30 connects to at least one PCIe endpoint device;
the access server connects to the processor and the PCIe endpoint device; and
Petition 870180144672, of 10/25/2018, p. 12/18
10/11 the access server is configured to receive a request to access the processor's PCIe endpoint device, and to return a response message from the processor access request regardless of whether access to the endpoint device PCIe is successful, where the access request response message is to indicate to the processor that the access server received the access request and to allow the processor to turn off a timer started for the access request after receiving the message response to the access request, in order to isolate access between the
10 processor and the PCIe endpoint device.
27. Access server, according to claim 26, characterized by the fact that the access server is further configured to access the PCIe endpoint device according to the access request.
28. Access server, according to claim 26 or 27, characterized by the fact that the access server is implemented by a direct memory access engine (Direct Memory Access, DMA); and the DMA engine is specifically configured to receive a data migration request sent by the processor, and in accordance with the data migration request to migrate specific data in a PCIe engine memory to a computer system memory or migrate specific data in the computer system memory to the PCIe endpoint device memory.
29. Access server, according to any of claims 26 to 28, characterized by the fact that the access server is still configured to perform for one of:
sending a first notification message to the processor, where the first notification message indicates that access to the PCIe endpoint device is successful; and
30 send a second notification message to the processor, where the second notification message indicates that access to the PCIe endpoint device has failed.
Petition 870180144672, of 10/25/2018, p. 13/18
[11]
11/11
30. PCIe exchanger, where the PCIe exchanger applies to a computer system, characterized by the fact that the computer system comprises a processor and a PCIe peripheral component interconnect express bus, and the PCIe bus co5 connects to at least one PCIe endpoint device;
a port upstream from the PCIe exchanger connects to the processor via the PCIe bus and a port downstream from the PCIe exchanger connects to the PCIe endpoint device via the PCIe bus; and
The access server as defined in any of claims 26 to 29, is embedded in the PCIe exchanger.
Petition 870180144672, of 10/25/2018, p. 14/18
1/8

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公开号 | 公开日

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EP2811413A4|2014-12-10|

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BR112013033792A2|2017-02-07|

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JP5953573B2|2016-07-20|

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EP3173936A1|2017-05-31|

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CN104335194A|2015-02-04|

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EP2811413A1|2014-12-10|

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JP2015519665A|2015-07-09|

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EP2811413B1|2016-10-19|

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AU2013263866A1|2014-12-04|

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CA2833940A1|2014-11-02|

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ES2610978T3|2017-05-04|

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法律状态:
2018-07-31| B06A| Patent application procedure suspended [chapter 6.1 patent gazette]|

---

2018-11-06| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|

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2018-12-04| B16A| Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 02/05/2013, OBSERVADAS AS CONDICOES LEGAIS. |

优先权:

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申请号 | 申请日 | 专利标题

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PCT/CN2013/075088|WO2014176775A1|2013-05-02|2013-05-02|Computer system, access method and apparatus for peripheral component interconnect express endpoint device|

---